Reflex C++

Reflex::SIMD

Hardware-accelerated 4-wide vector operations using SSE/NEON intrinsics under the hood. Useful for audio processing, geometry transforms, and any data-parallel computation.

SIMD Types

Reflex wraps platform SIMD registers (__m128 / NEON) into a clean, type-safe TypeV4<TYPE> template. Three aliases cover the common cases.

Type Aliases

AliasExpands To
FloatV4TypeV4<Float32> — 4× float
IntV4TypeV4<Int32> — 4× int
BoolV4TypeV4<Boolean> — 4× boolean mask
enum Boolean { kBooleanFalse, kBooleanTrue };

TypeV4<TYPE> Members

Data & Assignment

TYPE TypeV4::data; // Raw SIMD register
TypeV4<TYPE>& operator=(const TypeV4<TYPE>& value);
TypeV4<TYPE>& operator=(TYPE value); // Broadcast scalar
void Set(TYPE value); // Broadcast
void Set(TYPE a, TYPE b, TYPE c, TYPE d); // Set each lane

Compound Assignment

TypeV4& operator+=(const TypeV4& value);
TypeV4& operator-=(const TypeV4& value);
TypeV4& operator*=(const TypeV4& value);
TypeV4& operator/=(const TypeV4& value);

Lane Access

TYPE& operator[](UInt32 idx);
TYPE* GetData();
TYPE GetFirst(); // Lane 0
Tuple<TYPE,TYPE,TYPE,TYPE> Get(); // All 4 lanes

Store

void Store(TYPE* unaligned); // Store to unaligned memory

SIMD Operations

All operations work lane-by-lane on 4-wide vectors. Comparisons return BoolV4 masks that can be used with Select for branchless conditional logic.

Arithmetic

FloatV4 operator+(const FloatV4& a, const FloatV4& b);
FloatV4 operator-(const FloatV4& a, const FloatV4& b);
FloatV4 operator-(const FloatV4& value); // Negate
FloatV4 operator*(const FloatV4& a, const FloatV4& b);
FloatV4 operator/(const FloatV4& a, const FloatV4& b);
FloatV4 Modulo(const FloatV4& a, const FloatV4& b);
// IntV4 versions for +, -, *

Bitwise (IntV4)

IntV4 operator&(const IntV4& a, const IntV4& b); // AND
IntV4 operator|(const IntV4& a, const IntV4& b); // OR

Math Functions

FloatV4 Abs(const FloatV4& value);
FloatV4 Sign(const FloatV4& value);
FloatV4 Reciprocal(const FloatV4& value); // 1/x (fast approximate)
FloatV4 Invert(const FloatV4& value); // 1/x (precise)
FloatV4 SquareRoot(const FloatV4& x);
FloatV4 Exp(const FloatV4& value);
FloatV4 Exp2(const FloatV4& value);
FloatV4 Log(const FloatV4& value);
FloatV4 Log2(const FloatV4& value);
FloatV4 Pow(const FloatV4& x, const FloatV4& y);
FloatV4 ClipNormal(const FloatV4& value); // Clamp to [0, 1]
FloatV4 RoundDown(const FloatV4& value);
FloatV4 RoundNearest(const FloatV4& value);

Min / Max

FloatV4 Min(const FloatV4& a, const FloatV4& b);
FloatV4 Max(const FloatV4& a, const FloatV4& b);
IntV4 Min(const IntV4& a, const IntV4& b);
IntV4 Max(const IntV4& a, const IntV4& b);
IntV4 Abs(const IntV4& value);

Comparison

All comparisons return BoolV4 masks.

BoolV4 operator==(const FloatV4& a, const FloatV4& b);
BoolV4 operator!=(const FloatV4& a, const FloatV4& b);
BoolV4 operator<(const FloatV4& a, const FloatV4& b);
BoolV4 operator<=(const FloatV4& a, const FloatV4& b);
BoolV4 operator>(const FloatV4& a, const FloatV4& b);
BoolV4 operator>=(const FloatV4& a, const FloatV4& b);
// IntV4 versions for ==, !=, <, >

Mask Operations

Boolean Logic

BoolV4 And(const BoolV4& a, const BoolV4& b);
BoolV4 Or(const BoolV4& a, const BoolV4& b);
BoolV4 Not(const BoolV4& a);

Mask Queries

FunctionReturns
Any(mask)true if any lane is true
Full(mask)true if all lanes are true
Empty(mask)true if no lanes are true
Count(mask)number of true lanes
GetFlags(mask)bitmask of true lanes
GetFree(mask)index of first false lane

Conditional Select

TypeV4<TYPE> Select(const BoolV4& mask, const TypeV4<TYPE>& true_value, const TypeV4<TYPE>& false_value);
TypeV4<TYPE> Select(const BoolV4& mask, const TypeV4<TYPE>& true_value); // false → 0
TYPE SelectNot(const BoolV4& a, const TYPE& b);

Example

FloatV4 a, b;
a.Set(1.0f, 2.0f, 3.0f, 4.0f);
b.Set(4.0f, 3.0f, 2.0f, 1.0f);
auto result = a + b; // {5, 5, 5, 5}
auto mask = a < b; // {true, true, false, false}
auto selected = Select(mask, a, b); // {1, 2, 2, 1}